To extract a clock synchronized with recorded data in a typical conventional reproduction signal processor, the oscillation frequency of a VCO (Voltage Control Oscillator) is controlled in, e.g., Patent Document 1 by quantizing an inputted reproduction signal with a quantization means (A/D converter), calculating a frequency error and a phase error with a digital circuit based on reproduction data obtained by removing an offset component from quantization data with an offset adjustment circuit, smoothing the frequency error and the phase error with a loop filter, and converting an amount of digital correction to an analog value with a D/A converter. FIG. 2 shows a block structure of such a feedback clock generation circuit. By performing feedback-type control as described above, synchronization between a clock for driving the A/D converter as well as a digital portion and a reproduction signal is intended. For the decoding of data, synchronization can be provided between the clock and the quantized reproduction data. This allows data detection to be performed by a data detector based on the data.
In the field of, e.g., an optical disc, higher densities have been achieved with a CD, a DVD, and the like. Further, a higher reproduction speed has also been achieved. In a synchronous clock generation circuit in which a digital arithmetic operation is included in a feedback loop, such as a reproduction signal processor shown in FIG. 2, a pipeline process needs to be performed in order to implement a high-speed operation so that clock digital latency in a feedback loop for clock extraction increases. In a typical conventional phase comparator as shown in FIG. 19, a phase error is calculated using data when a reproduction signal zero-crosses so that the linear range of the phase comparator is from −π to +π. As a result, when the reproduction signal falls outside the linear range, phase inversion occurs. When the clock latency increases, the phase inversion frequently occurs to particularly significantly degrade the capture range (pull-in range) of the clock generation circuit, which is shown in FIG. 20.
On the other hand, in Patent Document 2, a phase detector is provided with the structure shown FIG. 21. The phase comparator of FIG. 21 has a structure different from a typical conventional structure, and generates a reference value by multiplying a previous phase error by a gain without fixing a timing of calculating a phase error to a zero-cross timing, and calculates a phase error with the timing with which inputted sampling data crosses the reference value. By providing the phase comparator with such a structure, it is possible to enlarge the linear range of the phase comparator and lessen the inversion level of phase inversion. This allows a significant improvement in pull-in characteristic. FIG. 22 shows the characteristics of the phase comparator shown in FIG. 21.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-8315
Patent Document 2: Specification of Japanese Patent No. 3889027